The present invention relates generally to the field of semiconductor devices, and more particularly to a method for reducing segregation and diffusion of halo implants into highly doped regions.
When transistor gate length is scaled down, the impact of the halo profile on device performance becomes more important. The halo profile not only determines the magnitude of the transistor short-channel-effect, but also impacts the transistor channel mobility, Cj, diode leakage, and drive current. Since the profile of the halo is mainly determined by its diffusivity, many super halo processes proposed earlier were centered on the use of disposable spacer, reduced thermal budget, or heavy ion species with low diffusivity. These approaches suffer various shortcomings, such as increased process complexity, reduced dopant activation level in silicon or poly gate, etc. The use of fluorine implant at different steps of the process has been studied for many years to improve pMOS NBTI, reduce hot-carrier damage and produce shallow boron highly doped drain (xe2x80x9cHDDxe2x80x9d) extension. These fluorine implants have not, however, been used to tailor the profile of the halo implants to provide different electrical characteristics in sub-50 nm transistors.
The present invention provides a method that allows the profile of the halo implants to be tailored to provide different electrical characteristics in sub-50 nm transistors. Moreover, the present invention reduces halo implant segregation and diffusion into highly doped regions of the transistor by using fluorine to produce super-halo for both nMOS and pMOS transistors. The fluorine-assisted halo process of the present invention produces a super-sharp halo profile and reduces halo dopant segregation into HDD by reducing halo dopant diffusivity. Furthermore, the degree of halo profile sharpness and the amount of dopant segregation can be tailored by varying the fluorine implant conditions. As a result, different transistor parametric requirements can be met, such as lowered junction capacitance (Cj) and improved Ion-Ioff characteristics, by trading off the sharpness of the halo and the smoothness of the junction.
The present invention provides a method for forming a transistor junction in a semiconductor wafer by implanting a dopant material into the semiconductor wafer, implanting a halo material into the semiconductor wafer, selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the semiconductor wafer at the selected dose and energy, activating the dopant material using a thermal process and annealing the semiconductor wafer to remove residual fluorine. The one or more characteristics of the transistor may include halo segregation, halo diffusion, the sharpness of the halo profile, dopant activation, dopant profile sharpness, drive current, bottom wall capacitance or near edge capacitance.
In addition, the present invention provides a method of fabricating a transistor by forming a gate dielectric over a semiconductor body, forming a gate electrode over the gate dielectric, forming an implant blocking spacer adjacent sidewalls of the gate electrode, forming a first doped region of a first conductivity type in the semiconductor body adjacent the implant blocking spacer, forming a halo region of a second conductivity type in the semiconductor body at least partially under the implant blocking spacer to form a halo in the semiconductor body, selecting a fluorine dose and energy to tailor one or more characteristics of the transistor, implanting fluorine into the halo region at the selected dose and energy, forming a sidewall spacer adjacent to the implant blocking spacer and forming deep source/drain region in the semiconductor body aligned to the sidewall spacer.
Other features and advantages of the present invention will be apparent to those of ordinary skill in the art upon reference to the following detailed description taken in conjunction with the accompanying drawings.